MODULE 1   :DIGITAL  DESIGN FUNDAMENTALS

              DIGITAL DESIGN

              NUMBER SYSTEM

              BOOLEAN ALGEBRA

              BASIC LOGIC GATES

              DIGITAL CIRCUITS

MODULE 2   :DIGITAL  DESIGN TECHNIQUES

             COMBINATIONAL LOGIC

             SEQUENTIAL LOGIC

             SEQUENTIAL CIRCUIT DESIGN

             STATE MACHINES

             TIMING ISSUES

MODULE 3   :VERILOG HDL

            INTRODUCTION OT XILINX ISE SYSNTHESIS &  MODELSIM             SIMULATOR TOOL

            VERILOG IMPORTANCE

            LANGUAGE ELEMENTS

            GATA LEVEL MODELING

            DATA FLOW MODELING

            BEHAVIORAL MODELING

            TASKS AND FUNCTIONS

            SIMULATION ISSUES

            SYNTHESIS ISSUES

            BLOCKING AND NON BLOCKING

            SYNTHESIS OF VERILOG CONSTRUCTS        

            VERILOG TEST BENCHES       

MODULE 4  :PLD – PROGRAMMABLE LOGIC DEVICES

            INTRODUCTION

            DESIGN FLOW FOR PLD DESIGN

            MEMORY IN PLD’S

            PLA & PAL

            COMPLEX PLD’S – CPLD

            FPGA – FIELD PROGRAMMABLE GATE ARRAYS

           COMPARATIVE  STUDY OF CPLD  v/s  FPGA.

MODULE 5  :IMPLEMENTATION AND VERIFICATION ON                    XILINX FPGA

                1.SEMI CUSTOM DESIGN

                2.FULL CUSTOM DESIGN